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Project Brief

Open Competition 3 - Electronics and Photonics

PowerFlow: Next-Generation Intellectual Property Technology for System-on-a-Chip Designs

Develop a system-on-a-chip architecture that blends the flexibility of fully programmable microprocessors with the high performance of function-specific processors, radically lowering design costs and speeding development of devices for embedded applications.

Sponsor: The Athena Group, Inc.

5522 NW 43rd St.
Suite B
Gainesville, FL 32653
  • Project Performance Period: 10/1/2003 - 4/30/2007
  • Total project (est.): $2,821,945.00
  • Requested ATP funds: $1,999,859.00

In this three year project, The Athena Group, Inc., aims for a major leap forward in the design and manufacture of digital signal processors (DSP), the semiconductors at the heart of digital video cameras, cellular phones, and a growing array of other electronic gear. On a single, hybrid chip, the company plans to achieve both the flexibility of programmable microprocessors and the superior performance of hard-wired, special-purpose processors. Success would free designers of a long-standing dilemma: whether to sacrifice increased speed and lower energy consumption for the ability to make changes should a mistake or failure be uncovered at a critical point during a product's development or market debut. This technical innovation would help to protect U.S. leadership in the multi-billion dollar integrated circuit industry, while increasing DSP throughput by a factor of more than 100 and significantly reducing energy requirements. If successful in bridging the gap between error-forgiving fully programmable microprocessors and performance-improving function-specific processors, the new system-on-a-chip (SOC) architecture would significantly reduce development-cycle times and costs. At the hub of the proposed system's architecture is a data transfer processor with multiple programmable interfaces linking it to cores, or clusters, of function-specific processors. The hub processor transfers data between cores and provides memory and other resources. Design and programming software that Athena will develop will enable chip designers to define, configure, and integrate function-specific processors. The software-orchestrated approach would eliminate the risky, manual design of hard-wired connectivity without compromising performance. Today, engineering costs for developing embedded processing solutions can cost millions of dollars, and every subsequent modification of hard-wired processors requires an expensive and time-consuming fabrication cycle. With the new Athena SOC architecture, far fewer design iterations would be required. Designers could build on or customize previously proven designs and flexibility is inherent with the Athena architecture. By powering only needed portions of the chip, the new architecture will also translate into significant reductions in operating power requirements, extending battery lifetimes and enabling greater device functionality. In addition, Athena s approach should result in higher levels of functional integration since the new architecture is designed for parallel multi-threaded operation. It not only will process individual data streams at high speeds but also process multiple streams concurrently. The project's technical risks are high. The company's approach to SOC design represents a significant technical departure from current methods used to improve performance in similar applications. ATP funding will enable Athena to accelerate development of its innovative technology to the proof-of-concept stage, overcoming technical risks and shortening time horizons that have deterred private funding sources.

For project information:
Pat Rugg, (352) 371-2567

ATP Project Manager
Gerald Castellucci, (301) 975-2435

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